The present invention relates to a semiconductor integrated circuit which has high integration density and is capable of reducing current consumption in a stand-by state.
As for a semiconductor integrated circuit in which current consumption in a stand-by state is very small, there is well known a CMOS circuit. When an input is at a high level, a P-channel MOS transistor is on, and an N-channel MOS transistor is on. When the discharge of a capacitive load of an output has been completed, an N-channel MOS transistor is turned off, and in this state, the power consumption can be disregarded. When the input is set at a low level, the P-channel MOS transistor is on, and the N-channel MOS transistor is off. When the charge of the capacitive load of the output has been completed, the P-channel MOS transistor is turned off, and even in this case, similarly the power consumption can be disregarded.
On the other hand, a semiconductor integrated circuit of high integration density which is designed in such a way that shrunken MOS transistors are used in an internal circuit within a chip, and an internal source voltage, which is lower than an external source voltage, is generated by a voltage dropping circuit (on-chip voltage limiter) provided in the chip in order to cope with the decrease of a breakdown voltage of the MOS transistor accompanying with the shrink, thereby to supply the internal source voltage to the internal circuit is heretofore described in U.S. Pat. No. 4,482,985 (issued to Itoh et al on Nov. 13, 1984 and assigned to the assignee of the present invention).
On the other hand, in U.S. Pat. No. 4,873,673 (issued to Hori et al on Oct. 10, 1989 and assigned to the assignee of the present invention) is disclosed a system which is designed in such a way that a rising speed of a transient current of an internal circuit just after applying a power is increased, while in order to control a peak value of the transient current, a current mirror circuit is connected between an external power source and an internal circuit to limit a current to be supplied to the internal circuit, and also the increase of the voltage, which is applied to the internal circuit, is clamped at a predetermined value by the negative feedback.
Recently, the fine pattern technology used for the semiconductor integrated circuit has been remarkably developed, and the processing dimension is approaching 0.1 .mu.m. As compared with the MOS transistor having a channel length of 1 .mu.m, even when a threshold voltage of the MOS transistor having a channel length of about 0.1 .mu.m is decreased, and also the voltage across a gate and a source of that MOS transistor is less than or equal to the threshold voltage, a drain current does not become zero. A leakage current in a subthreshold region in which that voltage across the gate and the source is less than or equal to the threshold voltage is called a subthreshold current.